Silicon tips have been proposed for use in memory storage systems. These systems are composed of CMOS or other electrical components, a tip or tip array, a scanning system, and a recording media such as a phase change, plastic, electric charge storage or ferroelectric media. In order to create a bit of stored information, the tip produces an electron flux, heat, contact pressure, and/or applied electric or magnetic field to the particular media to create a physical change. Given the importance of the tip to the storage system, it is desired that the tip have the flexibility to be integrated into standard Integrated Circuit (IC) manufacturing.
Silicon is advantageous for being used as a tip material as there is a large knowledge base on the material's characteristics and it is widely used in the IC industry. Micro and Nano scale devices using silicon can be created using existing processes and equipment. Electronic components of various types, including CMOS, can be integrated by using silicon as a substrate, thereby limiting interconnect length and component size.
There are limitations that make silicon less than ideal for tips in memory devices. Intrinsic silicon has a relatively high resistivity (1K ohm-cm) while standard doped (p or n) silicon has a resistivity of about 0.5–30 ohm-cm. Resistivity limits the amount of current that can be drawn through the tip used as an electron source. For applications involving electromagnetic fields and contact probes, high material resistance means higher applied voltages in order to obtain the proper field or tip temperature. Contact applications involving silicon tips are affected by tip wear, friction, and the tendency of silicon to adsorb contaminates such as water. Finally, the standard method to produce crystalline silicon tips requires process temperatures above the stability zone of electrical components. This higher temperature processing requires that any associated CMOS structures/devices be integrated into the process after the tip formation, thus adding additional complex processing steps and reducing efficient use of die area.